比利时专利BE1025218B1 PRINT HEAD PEN SETUP

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专利摘要:
Printhead pen arrangements are described. An exemplary printhead assembly includes an interface to place the printhead assembly in communication with a logic circuit. Furthermore, a logic circuit is described that is configured according to a pin arrangement, the pin arrangement comprising pin groups, each of the pin groups including a signal line and a reference voltage.
公开号:BE1025218B1
申请号:E2017/5563
申请日:2017-08-14
公开日:2018-12-12
发明作者:Dwight D. Dipert；Daniel F. Donato
申请人:Zih Corp.；
IPC主号:

专利说明:

PRINT HEAD PEN SETUP
Description field
This description mainly relates to media processing devices and more particularly to printhead arrangements.
Background
Some media processing devices include a printhead to generate media and / or machine readable indications on media. The printhead receives data and generates the indications based on the received data. The printhead generates the indications by, for example, placing ink on the media, transferring ink thermally to the media, applying energy to specific parts of the media and / or via another suitable printing technique.
Summary of the invention
According to an aspect of the invention, a printhead assembly is provided, comprising: an interface to place the printhead assembly in communication with a logic circuit; and a logic circuit configured in accordance with a pin arrangement, the pin arrangement comprising pin groups, each of the pin groups including a signal line and a reference voltage.
Advantageously, the pin arrangement can further have forty pins and eleven pin groups.
The pin arrangement may further contain ten data pins.
The pen arrangement can also contain five clock pins.
The pin arrangement may further comprise first and second latch pins. In the printhead assembly, the first latch pin can also be assigned to a first pin group and the second latch pin can be assigned to a second pin group
BE2017 / 5563. Advantageously, the pin arrangement may further comprise first and second strobe pins. The first strobe pin can be additionally assigned to a first pin group and the second strobe pin can be assigned to a second pin group. The pin arrangement may alternatively contain thirty pins and ten pin groups. The reference voltage may further be a first reference voltage and each of a plurality of pin groups may contain the first reference voltage and a second reference voltage that differs from the first reference voltage. The logic circuit can further implement a control unit for a printhead with heating elements.
According to another aspect, a media processing device is provided, comprising: a memory including machine-readable instructions; and a processor to execute machine-readable instructions to control a printhead assembly, the processor configured to communicate with the printhead assembly in accordance with a pin arrangement, the pin arrangement including pin groups and each of the pin groups having a signal line and a reference voltage contains. Advantageously, the pin arrangement can contain forty pins and eleven pin groups. The pin configuration may further contain ten data pins.
The present invention will be further explained with reference to figures and exemplary embodiments. Corresponding elements are indicated with corresponding reference numerals.
Brief description of the figures
FIG. 1 is a block diagram representative of an exemplary media processing apparatus that can use teachings of the description.
FIG. 2 is a perspective view of one
BE2017 / 5563 example implementation of the example media processing device from
FIG. 1.
FIG. 3 is a side view of internal components of the exemplary media processing apparatus of FIG. 2.
FIG. 4 is a perspective view of an exemplary printhead assembly shown in the exemplary media processing apparatus of FIG. 2 can be implemented.
FIG. 5 is a perspective view of an exemplary adapter connected with the exemplary printhead assembly of FIG. 4 can be implemented.
FIG. 6 is a table representative of a first exemplary pen arrangement constructed in accordance with teachings of the description.
FIG. 7 is a schematic diagram of a first exemplary connection type between the control unit of FIG. 1 and the printhead assembly of FIG. 1.
FIG. 8 is a table representative of a second exemplary pen arrangement constructed in accordance with teachings of the description.
FIG. 9 is a schematic diagram of a second exemplary connection type between the control unit of FIG. 1 and the printhead assembly of FIG. 1.
FIG. 10 is a table representative of a third exemplary pen arrangement constructed in accordance with teachings of the description.
FIG. 11 is a table representative of a fourth exemplary pen arrangement constructed in accordance with teachings of the description.
FIG. 12 is a block diagram of an exemplary logic circuit for implementing the exemplary control unit of FIG. 1, it
BE2017 / 5563 example interface of FIG. 1, the exemplary control unit of FIG. 1 and / or another logic circuit in accordance with teachings of this description.
Detailed description
Some media processing devices, such as printers, serve to convert electronic data to media indications. The conversion process performed by such media processing devices includes, among other operations, internal communication of the electronic data and interpretation of the electronic data. An exemplary printer includes, for example, a control unit (e.g., a logic circuit such as a processor or a programmable gate array) to receive and / or process the electronic data (e.g., format), a printhead to generate media indications based on the electronic data, cable (s) and / or connector (s) to send the electronic data from the control unit to the print head and interface (s) to facilitate the reception and / or interpretation of the electronic data at the print head.
Since speed is usually a significant performance metric for such a media processing device, the speeds at which communication components of the media processing device transmit, receive, and process the electronic data are important factors. Example pin arrangements described herein group pins and thus corresponding cables in communication with the pins, in a manner where the speed with which the media processing devices convert electronic data into indications on media improves. As described in detail below, each pin group of exemplary pin arrangements described herein contains at least one signal pin and at least one reference signal (e.g., ground or any sufficiently coupled reference voltage such as five (5) volt power connection (VDD)). A pen that
BE2017 / 5563 is designated as the reference voltage is one that is coupled to a constant voltage. Example reference voltages include ground (GND) and a fixed current (DC) energy connection to, for example, five (5) volts. A pin designated as a signal pin is one that is linked to a source with non-constant or changing values. Example signal pins include pins assigned to a clock line, a data line, a latch line, a straw line, and a sensor line (e.g., a line coupled to a thermistor).
By including at least one reference voltage, such as ground, in each group of pins (and thus cables) through which one or more signals are communicated, an effective loop region between a signal (e.g., a high-speed digital data signal) and a return (e.g. ground or other reference voltage), thereby reducing the transit time of signals through the circuit. For example, as described in detail below, exemplary pin arrangements described herein provide a better clock speed associated with communication of electronic data via cables (e.g., a 50.8 cm (20 inch) ribbon cable ending with isolation displacement connections (IDC)). Additionally, as described in detail below, exemplary pin arrangements described herein provide greater data rates associated with communication of electronic data via cables. As a result, the exemplary pen arrangements described herein are capable of processing data faster and thus able to convert electronic data to media indications faster.
Another key factor for media processing devices are the potentially adverse effects of electromagnetic interference (EMI) caused by the electronic transmission that takes place via, for example, the cable (s) connecting the control unit and the printhead. An exemplary adverse effect caused by EMI is cross-talk cross-talk where electromagnetic radiation from a first wire of a cable directly interferes with a signal across a second wire of the same
BE2017 / 5563 cable and / or another signal sent over a wire or wires from another cable. Additionally or alternatively, the susceptibility of circuits and components to surrounding electromagnetic radiation can adversely affect the functionality of the circuits and / or components. Furthermore, levels of electromagnetic radiation can exceed limits set by, for example, a standard, and thereby bring the corresponding device out of compliance with the standard. Although exemplary complications and challenges associated with EMI are described herein, additional or alternative problems may arise through EMI.
Example pin arrangements described herein reduce or eliminate EMI and thus improve the performance of the components that would otherwise be affected. As described in detail below, exemplary pin arrangements described herein enable a physical layout (e.g., spatial relationship) between communication components (e.g., cables and / or) that, for example, reduces or eliminates cross-talk between components. Example pin arrangements described herein include pin groups with at least one signal pin and at least one reference voltage (e.g., ground or VDD) to provide a reduced effective loop area, thereby reducing induction and a more consistent impedance for high-speed signal lines (e.g., data lines and / or clock lines) is created. With the lower induction provided by examples described herein, interference (e.g., joint coupling) between signals is reduced. In addition, because exemplary pin arrangements reduce or eliminate EMI described herein, devices that perform examples described herein are better able to meet, for example, standards that set limits on electromagnetic radiation.
FIG. 1 is a block diagram of an exemplary media processing apparatus 100 including teachings from this description
BE2017 / 5563 can be implemented. The exemplary media processing apparatus 100 shown in FIG. 1 includes a control unit 102 and a control unit 110. Alternative embodiments of the exemplary media processing apparatus 100 of FIG. 1 contain one or more additional or alternative elements, processes and / or devices. Additionally or alternatively, the exemplary control unit 102 and / or the exemplary control unit 110 of FIG. 1 be combined, distributed, redesigned or omitted. The exemplary control unit 102, the exemplary control unit 110 and / or more generally, the media processing apparatus 100 of FIGS. 1 and / or 2 is / have been implemented in hardware, software, firmware and / or a combination of hardware, software and / or firmware. In some examples, the exemplary control unit 102 and the exemplary control unit 110 are implemented by a logic circuit (e.g., the exemplary logic circuit of FIG. 10). As used herein, the term "logic circuit" is expressly defined as a physical device that includes at least one hardware component that is configured (e.g., through operation in accordance with a predetermined configuration and / or through execution of stored machine-readable instructions ) to control one or more machines and / or perform operations of one or more machines. Examples of a logic circuit include one or more processors, one or more coprocessors, one or more microprocessors, one or more control units, one or more digital signal processors (DSPs), one or more integrated circuits for specific applications (ASICs), one or more field programmable gate arrays (FPGAs), one or more micro-controller units (MCUs), one or more hardware accelerators, one or more computer chips for special purposes and one or more system-on-a-chip (SoC) devices. Some exemplary logic circuits, such as ASICs or FPGAs, are specifically configured hardware that performs operations. Some example logical
BE2017 / 5563 circuits are hardware that executes machine-readable instructions to perform operations. Some exemplary logic circuits include a combination of specifically configured hardware and hardware that executes machine-readable instruction.
The exemplary media processing apparatus 100 of FIG. 1 includes a control unit 102 configured to control certain components of the media processing apparatus 100. In the illustrated example of FIG. 1, the control unit 102 is a logic circuit configured to perform printing functions. The exemplary control unit 102 of FIG. 1 is implemented by any suitable logic circuit such as, for example, one or more processors, microprocessor (s), coprocessor (s) and / or integrated circuit (s) (e.g. an ASIC (application specific integrated circuit for specific application), an FPGA ( field programmable gate array), etc.). In some examples, the control unit 102 is configured to execute instructions stored in a memory 104 of the media processing apparatus 100. The exemplary memory 104 of FIG. 1 is implemented, for example, by volatile and / or non-volatile memory that is either fixed or removable. The exemplary memory 104 of FIG. 1 is configured to store information, data, applications, instructions and / or the like to enable the control unit 102 to perform printing functions in addition to operations.
The exemplary driver 102 of FIG. 1 receives data representative of print jobs (e.g., print jobs) from memory 104 and / or an external data source 106. Examples of external data sources include a parent device, a parent system, a network device, and a removable storage system. In the illustrated example of FIG. 1, the control unit 102 processes the received data such that the data is usable to print indications on media. The control unit 102 of FIG. 1 makes for example
BE2017 / 5563 use of a print engine to generate print data lines (e.g., directly or based on a bit map image) based on the received data.
In the example of FIG. 1, the control unit 102 sends the print data lines (or any other type of data suitable for printing indications on media) and control signals (e.g., a latch signal and a strobe signal) to a printhead assembly 108 of the media processing apparatus 100. The exemplary printhead assembly 108 includes a control unit 110 and a printhead 112. The exemplary control unit 110 of FIG. 1 is implemented by a logic circuit configured to control one or more operations of the printhead 112, so that the printhead 112 generates indications on media in accordance with the received data and control signals. In the example of FIG. 1, the printhead 112 uses energy from an energy source 114 of the media, processing system 100, to generate indications on the media.
To enable receipt of the electronic data and control signals from the printhead assembly 108 and to enable handling of the electronic data by the control unit 110, the exemplary printhead assembly 108 includes an interface 116. In the illustrated example, the interface 116 is configured to communicate with a control unit 102 in accordance with the pen arrangement 118. In some examples, the data representative of the pen positions arranged in the pen arrangement 118 are stored in the memory 104. In some examples, the data is representative of the the pen we sing arranged in the pen arrangement 118 is additionally or alternatively stored in a memory present in the printhead assembly 108. The pin arrangement 118 of FIG. 1 defines which pins are dedicated to or assigned to specific types of signals used by the control unit 102 to transmit data or instructions
BE2017 / 5563 to provide the print assembly 108. Exemplary pen arrangements described herein that improve media processing devices are described below in connection with FIGS. 6-9.
FIG. 2 illustrates an exemplary embodiment of the media processing apparatus 100 of FIG. 1. The exemplary media processing apparatus 100 of FIG. 2 is an independent unit. However, teachings of this disclosure can be used in integrated media processing systems such as, for example, an ATM (ATM), a kiosk, or a point-of-sale device. In the illustrated example of FIG. 2, the media processing apparatus 100 uses a thermal printing technology (e.g., direct thermal printing technology, thermal transfer printing technology and / or ink sublimation thermal printing technology) to generate media indications. As an example, the media processing apparatus 100 of FIG. 2 are a thermal label printer. However, teachings of this description can be applied to any suitable printing technique.
The exemplary media processing apparatus 100 of FIG. 2 contains a housing 202 with a door 204. As shown in FIG. 2, the door 204 is in a closed operational state in which access to the internal components is excluded. In addition to preventing dirt, dust and foreign objects from entering an internal cavity of the media processing device 100 and possibly contaminating consumables or electronics, the door 204 can also reduce noise and prevent accidental contact of sensitive components. The exemplary door 204 of FIG. 2 is hingedly connected to a frame of the media processing apparatus 100 through hinges 206 so that the door can be opened to provide access to the internal components of the media processing apparatus 100. As described below in accordance with FIG. 3, the frame includes a chassis on which various components of the media processing device are mounted. As described below
BE2017 / 5563 according to FIG. 3, a printing mechanism attached to the chassis generates indications on media supplied to the printing mechanism by components attached to the chassis. The printing mechanism ejects the media at an exit 208 that is located along a front surface 210 of the housing 202.
FIG. 3 shows a side view of a portion of the media processing apparatus 100 of FIG. 2 with the door 204 removed. A view similar to FIG. 3 is available when the door 204 is open. As in FIG. 3, a chassis 300 supports internal components comprising a media axis (not shown), a plurality of guide components (e.g., rollers guiding media and / or ribbon), a ribbon feed shaft 302, a ribbon pickup shaft 304, a transfer sensor 306, a plate assembly 308 and a printing mechanism 310. In the illustrated example of FIG. 3, the printing mechanism 310 includes a support structure 312 and removable covers 314 and 316 that shield the printing mechanism 310. The media axis (not shown) is adapted to hold a spool of media that is supplied to the printing mechanism 310 and out of the output 208.
When the media processing apparatus 100 of FIG. 3 is adapted for thermal transfer printing, thermal transfer media are attached to the media axis and an ink ribbon is attached to the ribbon feed axis 302. Therein, the ribbon feed shaft 302 is arranged to hold a spool of unused ribbon. The ink ribbon is fed from the ribbon feed shaft 302 to the printing mechanism 310, which uses the ink ribbon to generate indicia on the media of the media axis, which is simultaneously supplied to the printing mechanism 310. Ribbon that is used moves through the printing mechanism 310 and is guided to the ribbon take-up shaft 304. Therein, the ribbon take-up shaft is arranged to hold a spool of ribbon that has been used. The exemplary printing mechanism 310 of FIG. 3 generates indications on the media at a nip formed at a
BE2017 / 5563 roller of the plate assembly 308 and the print head 112. In particular, the printing mechanism 310 provides via the control unit 110 of FIG. 1 selectively energizes heating elements (e.g., dots) from the printhead 112 to provide heat to the ink ribbon in accordance with, for example, received print line data. At points on the thermal transfer media near heating elements of the printhead 112 to which energy has been supplied, ink is transferred from the ink ribbon to the thermal transfer media, thereby generating indications on the media representative of the print line data. Depending on the type of media, a threshold value of joules per square inch or Watt second per square inch is required to transfer the ink from the ribbon to the media.
When the media processing apparatus 100 is adapted for direct thermal printing, direct thermal media (e.g., labels containing heat sensitive dye (s)) are attached to the media axis (not shown). Direct thermal media (e.g., thermochromic paper) are designed and manufactured so that when a threshold amount of energy is applied to the media, a chemical reaction takes place in the media that causes a change in appearance (e.g., a change in color of white to black). In the example of FIG. 3, the direct thermal media is fed from the media axis to the printing mechanism 310. In such cases, the direct thermal media is not accompanied by an ink ribbon by the printing mechanism 310. Instead, in the direct thermal mode, the print head 112 directly selectively applies heat to the direct thermal media that is passed over the print head, thereby a change in appearance of the media is caused at selective locations of the direct thermal media. Depending on the type of media, a threshold value of joules per square inch or Watt second per square inch is required to cause a chemical reaction in the direct thermal media to
BE2017 / 5563 thereby causing a change in appearance of a single or multiple number of parts of the media.
In FIG. 4 is an exemplary application of the printhead assembly 108 of FIG. 1 shown. The exemplary printhead assembly 108 is supported by the exemplary print mechanism 310 of FIG. 3. The exemplary printhead assembly 108 includes the control unit 110 (FIG. 1) and a printhead 400. The exemplary printhead 400 has a plurality of heating elements referred to as dots. The control unit 110 is implemented by a logic circuit adapted to control the heating elements of the printhead 400. The control unit 110 is implemented, for example, as a programmable gate array or as a processor capable of executing machine-readable instructions stored in a memory. In accordance with data control signals received from the control unit 102 via the interface 116, the control unit 110 of the printhead assembly 108 selectively energizes the dots of the printhead 400 to change the appearance of the media passed over the printhead 400 cause. The dots of the exemplary printhead 400 of FIG. 4 are linearly arranged. Depending on the content to be printed, different dots for a given line can be switched on or off. For example, if a solid line is to be printed above the media, all points on the printhead 400 are turned on to print that line as a solid line of dot images. The supply of energy to the dots is called strobing the dots and the time required to strok dots for a specific printing event is called the strobe time. Each line of a given print job can be printed by moving the media relative to the printhead 400 (e.g., via a motor) and by changing which dots are turned on and which dots are turned off. The speed at which the media is printed is often measured in inches per second
BE2017 / 5563 (ips), which can be related to the line stroking time needed to print individual lines in a print job. A dot status refers to whether or not the corresponding dot is supplied with energy. A dot status of "on" or "1" indicates that the corresponding dot must be supplied with energy, while a dot status of "off" or "0" indicates that the corresponding dot must not be supplied with energy.
The dots of the printhead 400 are strobed by control signals received at the printhead assembly 108 from the control unit 102 of the media processing apparatus 100. For example, the control unit 102 implements a print engine that formats electronic data for delivery to the printhead assembly 108 and around the formatted electronic data to the printhead assembly 108. In other words, the printhead assembly 108 receives print job information (e.g., print data lines and control signals) and the print head 400 generates media indications based on the received print job information.
To receive the print job information, the exemplary printhead assembly 108 of FIG. 4 removably placed in communication with the control unit 102 of the media processing apparatus 100 via the interface 116 (FIG. 1). In the example shown, the arrangement and structure of the interface depends on how the printhead assembly 108 is coupled to the control unit 102 of the media processing apparatus 100. In some examples, the printhead assembly 108 is placed in communication with the control unit 102 via an adapter . FIG. 5 illustrates an exemplary adapter 500 capable of placing the printhead assembly 108 in communication with the control unit 102 of the media processing apparatus 100. In such examples, the exemplary adapter 500 of FIG. 5 mounted on an element (e.g., a printhead carrier) of the printing mechanism 310 (FIG. 3). It
BE2017 / 5563 printhead assembly 108 of FIG. 4 is removably coupled to the exemplary adapter 500 in a single operation or movement by having a female connector 502 of the adapter 500 and a counterpart male connector 402 of the printhead assembly 108 engaged as a pair or disconnected. The exemplary printhead assembly 108 of FIG. 4 can be installed in and removed from the media processing apparatus 100 to, for example, replace, clean or inspect the printhead assembly 108. The exemplary female connector 502 of the adapter 500 includes alignment arms 504 and 506 which are adapted to be received on alignment receiving parts 404 and 406 of the printhead assembly 108. The alignment arms 504 and 506 of the adapter 500 cooperate with the alignment receiving parts 404 and 406 to establish and maintain alignment between the adapter 500 and the printhead assembly 108. The exemplary female connector 502 of the adapter 500 includes a plurality of inputs 508 adapted to connect to (e.g., link to) counterpart plugs 408 of the exemplary male connector 402 of the printhead assembly 108. Accordingly, a multiple number of electrical connections established via the single engagement of the adapter 500 and the printhead assembly 108. Further, a multiple number of electrical connections are simultaneously broken through the single disconnection of the adapter 500 and the printhead assembly 108.
The exemplary adapter 500 FIG. 5 includes an energy input connector 510 and a data input connector 512. In some examples, the example adapter 500 includes a different number of energy input connectors and / or a different number of data input connectors. The exemplary energy input connector 510 of FIG. 5 is connected to (e.g., via a single or multiple number of cables or directly to a circuit board) a power source
BE2017 / 5563 of the example media processing apparatus 100. The example data input connector 512 of FIG. 5 is connected to (e.g., via a single or multiple number of cables or directly to a circuit board) a data source such as, for example, the control unit 102 of the media processing apparatus 100 and / or an external data source (e.g., a data source 106 of FIG. 1) .
In the illustrated example of FIG. 5, the energy input connector 510 and the data input connector 512 are attached to a circuit board 514. The inputs 508 of the female connector 502 are electrically connected to the energy input connector 510 and the data input connector 512 via the circuit board 514. Accordingly, when connected to the male connector 402 of the printhead assembly 108, the adapter 500 of FIG. 5 receives energy and data from the respective sources of the media processing apparatus 100, to the printhead assembly 108. The printhead assembly 108, as such, receives the energy required to function (e.g., selectively energizes thermal elements of the printhead 400), the data representative of the indications to be generated on the media and the control signals used to control the printhead 400. Example pen arrangements described herein that improve communication and data processing through these connectors are described below in connection with FIGS 6-9.
Although the exemplary connector 502 of the adapter 500 of FIG. 5 is described as feminine and the exemplary connector 402 of the printhead assembly 108 of FIG. 3 if male is described, the connector 502 of the adapter 500 can also be arranged as a male connector and the connector 402 of the printhead assembly 108 can be arranged as a female connector. The electrical connections between the adapter 500 and the
BE2017 / 5563 printhead assembly 108 can be achieved via any suitable relationship between the connectors. In addition, the example adapter 500 may include any suitable additional or alternative type (s) of connector (s).
In some examples, the printhead assembly 108 is removably placed in communication with the control unit 102 of the media processing apparatus 100 without the adapter 500. In such cases, the exemplary connector 402 of FIG. 4 coupled to the control unit 102 of the media connection device 100 (e.g., via a single or multiple number of cables).
As described above, there are various possible ways of bringing the printhead assembly 108 into communication with the control unit 102. Examples described herein include pen arrangements for specific cases where the printhead assembly 108 is in communication with the control unit 102. In some examples, the pen arrangements described herein are stored on a memory of the printhead assembly 108. In some examples, the pen arrangements described herein are stored on the memory 104 of the media processing apparatus 100. In the illustrated examples, the control unit 110 is implemented by an FPGA configured according to the pen arrangement on the memory. 104 of the media processing device 100 is stored. Additionally, the control unit 102 (FIG. 1) is aware of the exemplary pin arrangement so that the control unit 102 provides data and control signals to the control unit 110 in accordance with the arrangement of the control unit 110. In other words, the printhead assembly 108 is arranged to transmit data and control signals from the control unit. receive control unit 102 in accordance with a specific pin arrangement known for the control unit 102.
FIG. 6 is a first exemplary pin arrangement 600 for an exemplary communication arrangement shown in FIG. 7. FIG. 8 is one
BE2017 / 5563 second exemplary pin arrangement 800 for an exemplary communication arrangement shown in FIG. 9. The upcoming discussion about FIGS. 6-9 refer to the media processing apparatus 100 and other elements of FIGS. 1-5 described above. However, the exemplary pin arrangements described herein can be implemented in any suitable device. For example, while FIG. 7 described below is conjugated with the exemplary adapter 500 of FIG. 5, the exemplary pin arrangement in FIG. 6 can be used with any suitable adapter if such an adapter is implemented in a corresponding media processing device. Additionally, although the example of FIG. 7 describes specific type of connectors, the exemplary pin arrangement described in FIG. 6 may be used in conjunction with any suitable type of connector.
In the example of FIG. 7, the control unit 102 is coupled to the adapter 500 (FIG. 5) via a 40-pin connector 700. In the illustrated example of FIG. 7, the 40 pin connector 700 includes a 20-inch ribbon cable and a first and a second fitting. In the illustrated example of FIG. 7, the first fitting of the 40-pin connector 700 is removably coupled to a 40-pin head associated with the control unit 102 and the second fitting is removably coupled to a 40-pin head of the adapter 500. Additionally, the energy source is 114 (FIG. 1) coupled to the adapter 500 via an energy connector 702. As described above, relationship with FIGS. 4 and 5, the printhead assembly 108 is removably coupled to the adapter 500 so that the printhead assembly 108 receives data, control signals, and energy through the adapter 500. The data connector of the adapter 500 is coupled as an example to elements of the control unit 110 as the printhead assembly 108 with the adapter 500 is coupled.
The exemplary pin arrangement 600 of FIG. 6 contains destinations for each of the forty (40) pins of the exemplary connections depicted
BE2017 / 5563 in FIG. 7. The exemplary pin arrangement 600 of FIG. 6 contains groups of pins shown with a shared hatch in FIG. 6. In the example of FIG. 6 contains a first group of pins 1-7, a second group contains pins 813, a third group contains pins 14-20, a fourth group contains pins 2127, a fifth group contains pins 28-34 and a sixth group contains pins 3540.
In the exemplary pin arrangement 600 of FIG. 6, pin 1 is assigned to a strobe signal line. As described above, the print head 112 is stripped when the heating elements are to be supplied with energy. Accordingly, a pulse is generated on the strobe signal line when the selected heating elements on the printhead 112 are to be energized. Additionally, pin 32 is assigned to a strobe signal line. As such, the exemplary pin arrangement 600 of FIG. 6 a first strobe pin assigned to one of the pin groups and a second strobe pin assigned to a different pin group than the first strobe pin.
In the exemplary pin arrangement 600 of FIG. 6, pins 2, 7, 10, 15, 18, 21, 23, 26, 31, 33 and 38 are assigned to a first reference voltage referred to in FIG. 6 is referred to as earth (GND). In particular, each of the pin groups in the exemplary pin arrangement 600 of FIG. 6 at least one pin assigned to the first reference voltage. Furthermore, each of the four pin groups in the exemplary pin arrangement 600 of FIG. 6 more than one pin assigned to the first reference voltage.
In the exemplary pin arrangement 600 of FIG. 6, pin 3 is assigned to the data signal line to receive data in accordance with print job information. In the illustrated example, the data received via data signal lines is used by the control unit 110 of the printhead assembly 108 to determine which of the heating elements is to be supplied with energy. What
BE2017 / 5563 means that the data received via the data signal lines are representative of the indications to be generated by the printhead 112. As an example, bits are loaded into registers of the controller 110 in accordance with the information received on the data signal lines. In the exemplary pin arrangement 600 of FIG. 6, pins 4, 13, 14, 19, 25, 29, 30, 34 and 35 are also assigned to data signal lines. In particular, each of the pin groups in the exemplary pin arrangement 600 of FIG. 6 at least one data signal line pen. The use of a multiple number (e.g., ten (10)) data signal lines set in the exemplary pin arrangement 600 of FIG. 6 allows increased throughput (e.g., 250 Mbits / second) to, for example, increase the speed at which data is supplied to the register of the controller 110.
In the exemplary pin arrangement 600 of FIG. 6, pin 5 is assigned to a second reference voltage line shown in FIG. 6 is referred to as VDD. In the illustrated example, the VDD lines are 5-volt energy connections that can be used by circuits of the printhead 112. In the exemplary pin arrangement 600 of FIG. 6 the pins 12, 28 and 36 are also assigned as VDD lines. Although the VDD pins and the GND pins are shown separately in FIG. 6, each of the VDD pins and the GND pins provides a reference voltage and can therefore be referred to as reference voltages, reference pins, reference signals or reference pins.
In the exemplary pin arrangement 600 of FIG. 6, pin 6 is assigned to a printhead clock signal line. Pins 11, 22, 27 and 37 are also assigned to a printhead clock signal line in the example of FIG. 6. The printhead clock signal lines are utilized by the control unit 110 to control operation of the printhead 112. In particular, the exemplary pin arrangement 600 of FIG. 6 a multiple number (e.g., five (5)) clock signal lines that lowers the capacitive load on each clock signal
BE2017 / 5563 (e.g., to 75 pF) and thus limits signal degradation and higher (e.g., 25
MHz) allows signal frequency.
In the exemplary pin arrangement 600 of FIG. 6, pin 8 is assigned to a signal line designated as a serial data line (SDA line) and pin 9 is assigned to a signal line designated as a serial clock line (SCL). In the illustrated example, the SCL line and the SDA line are used to communicate with (e.g., via I2C) a single or multiple number of logic circuits mounted on the printhead 112. For example, the SCL line and the SDA line are used to communicate with an EEPROM mounted on a circuit board of the printhead assembly 108. In some examples, the EEPROM stores information unique to the printhead 112. In some examples, the SDA line and the SCL line used to communicate with a security chip of the printhead 112 to prevent, for example, counterfeiting of the printhead 112.
In the exemplary pin arrangement 600 of FIG. 6, pin 16 is assigned to a "Block Enable Out" (B.E.O.) signal line that implements a safety feature that prevents the printhead elements from being turned on during power on or off.
In the exemplary pin arrangement 600 of FIG. 6, pin 17 is assigned to a latch signal line. The latch signal controls the locking and unlocking of the registers of the control unit 110 so that data for one print line is loaded simultaneously. In particular, the exemplary pin arrangement 600 of FIG. 6 shows a first and second latch signal pin, namely pin 17 that is assigned to one of the pin groups and pin 24 that is assigned to a different pin group than pin
17. The use of a plurality of latch signal lines in the exemplary pin arrangement 600 of FIG. 6 reduces the capacitive load.
In the exemplary pin arrangement 600 of FIG. 6, pin 39 is assigned to a printhead temperature signal line. The control unit 102 receives data from the temperature signal line and interprets the data
BE2017 / 5563 to determine a single or multiple number of temperature measurements of the printhead 112. In some examples, the data provided by the temperature signal line is generated by a sensor (e.g., a thermistor) mounted on the printhead 112. Pin 40 is assigned as a printhead temperature return (PHTEMP RTN), which is a reference voltage to provide a return line for the temperature signal line assigned to pin 39. That is, pin 40 is coupled to a reference voltage.
Regarding the grouping of pins shown in the example of FIG. 6, the pin arrangement 600 alternates at least one reference voltage (e.g. GND, PHTEMP RTN or VDD) with signal lines. Specifically, each of the groups in the exemplary pin array 600 contains at least one reference voltage and at least one signal line (e.g., PHTEMP, latch, strobe, data, clock, or B.E.O.). Alternating the reference voltages in this manner through the pin arrangement 600 possible lower induction paths required for higher speed signaling. The pin arrangement 600 of FIG. For example, 6 provides for increased bandwidth (e.g., 350 MHz) for clock signal lines and data loss lines with reduced loss (e.g., -3 db). Furthermore, the grouping makes pins as set in the exemplary pin arrangement of FIG. 6 Efficient combing of the cable is possible, which improves the mechanical penetration of the cable. The exemplary pin arrangement 600 of FIG. 6, for example, makes it possible to comb the cable in accordance with the groups set in FIG. 6 so that the cable is combed into six groups, with some having seven lines and others having six lines (e.g., 7-6-7-7-7-6). Since each group or cable bundle contains at least one reference voltage, the effective loop area between the signal lines and the corresponding return (e.g., ground) decreases. This is particularly advantageous when the individual cables are combed and separated, in which case, in the absence of the exemplary pin arrangement described herein, a
BE2017 / 5563 single shared reference voltage across different bundles would increase the effective loop area. The reduced loop area provided by the pin arrangement described herein lowers induction and creates a more consistent impedance for, for example, the high-speed signal lines (e.g., a digital data line). As such, with a lower induction, the interference (e.g., interconnection) between signals is reduced.
In some examples, the first pin (s) are deliberately isolated from the second pin (s) by assigning the first pin (s) to a first group and the second pin (s) to a second group that is different from the first group. For example, because a high-speed signal line, such as PHCLK, couples energy to a lower-voltage analog signal line (e.g., PHTEMP), some examples described herein isolate the high-speed signal lines from the lower-voltage analog signal lines by assigning the signals to different groups.
FIG. 8 is a second exemplary pin arrangement 800 for an exemplary communication arrangement depicted in FIG. 9. The exemplary communication arrangement of FIG. 9 does not include an adapter between the printhead assembly 108 and the control unit 102. Instead, the control unit 102 (FIG. 1) of the example of FIG. 9 coupled to the printhead assembly 108 via a 30-pin connector 900. In the illustrated example of FIG. 9, the 30-pin connector 900 includes a 20-inch ribbon cable and a first and second plug. In the illustrated example of FIG. 9, the first plug of the 30-pin connector 900 is removably coupled to a 30-pin header associated with the control unit 102, and the second plug is removably coupled to a 30-pin header of the printhead assembly 108. Additionally, the power source is 114 (FIG. 1) coupled to the printhead assembly 108 via an energy connector 902. The printhead assembly 108 is removably coupled to the control unit 102 so that the printhead assembly 108 includes data, control signals, and energy
BE2017 / 5563.
The exemplary pin arrangement 800 of FIG. 8 contains destinations for each of the thirty (30) pins of the exemplary connections depicted in FIG. 9. The exemplary pin arrangement 800 of FIG. 8 contains groups of pins depicted with a shared hatch in FIG. 8. In the example of FIG. 8 contains a first group of pins 1-8, a second group contains pins 9-14, a third group contains pins 15-20, a fourth group contains pins 21-26 and a fifth group contains pins 27-30.
In the exemplary pin arrangement 800 of FIG. 8, pin 1 is assigned to a B.E.O. signal line that prevents the printhead elements from turning on during power on or off.
In the exemplary pin arrangement 800 of FIG. 8, pin 2 is assigned to an SDA signal line and pin 3 is assigned to an SCL signal line.
In the exemplary pin arrangement 800 of FIG. 8, pin 4 is assigned to a first reference voltage, in FIG. 8 referred to as VDD. In the example shown, the VDD lines are 5-volt energy connections. In the exemplary pin arrangement 800 of FIG. 8, pin 7 is also assigned to the first reference voltage.
In the exemplary pin arrangement 800 of FIG. 8, pin 5 is assigned to a latch signal line. The latch signal controls the locking and unlocking of the registers of the control unit 110 so that data for one print line is loaded simultaneously. In particular, the exemplary pin arrangement 800 of FIG. 8 a first and second latch signal pin, namely pin 5 assigned to one of the pin groups and pin 26 assigned to a different pin group than pin 5. The use of a multiple number of latch signal lines in the exemplary pin arrangement 800 of FIG. 8 reduces the capacitive load.
In the exemplary pin arrangement 800 of FIG. 8, pin 6 is assigned to a strobe signal line. As described above, the print head 112 is stripped when the heating elements need energy
BE2017 / 5563. Accordingly, a pulse is generated on the strobe signal line when selected heating elements on the printhead 112 are to be energized. Additionally, pin 27 is assigned to a strobe signal line. As such, the exemplary pin arrangement 800 of FIG. 8 a first strobe pin assigned to one of the pin groups and a second strobe pin assigned to a different pin group than the first strobe pin.
In the exemplary pin arrangement 800 of FIG. 8, pin 8 is assigned to a data signal line to receive data in accordance with print job information. In the illustrated example, the data received via data signal lines is used by the control unit 110 of the printhead assembly 108 to determine which of the heating elements is to be supplied with energy. Which means that the data received via the data signal lines are representative of the indications to be generated by the printhead 112. For example, bits are loaded into registers of the controller 110 in accordance with the information received on the data signal lines. In the exemplary pin arrangement 800 of FIG. 8, pins 9, 14, 15, 17, 18, 23 and 24 are also assigned to data signal lines. The use of a multiple number (e.g., eight (8)) data signal lines set forth in the exemplary pin arrangement 800 of FIG. 8 allows increased transmission (e.g., 200 Mbits / second) to, for example, increase the speed at which data is supplied to the registers of the controller 110.
In the exemplary pin arrangement 800 of FIG. 8, pins 10, 13, 16, 19, 22, 25, 28 are assigned to a second reference voltage shown in FIG. 8 is referred to as GND.
In the exemplary pin arrangement 800 of FIG. 8, pin 11 is assigned to a printhead clock signal line. Pins 12, 20 and 21 are also assigned to a printhead clock signal line in the example of FIG. 8. The
BE2017 / 5563 printhead clock signal lines are utilized by the control unit 110 to control operation of the printhead 112. In particular, the exemplary pin arrangement 800 of FIG. 8 shows a multiple number (e.g., four (4)) clock signal lines that indicate the load on, for example, a clock control unit of the exemplary control unit 102 of FIG. 7 (e.g. up to 60 pF), thereby limiting signal degradation and allowing a higher (e.g., 25 MHz) signal frequency.
In the exemplary pin arrangement 800 of FIG. 8, a pin 29 is assigned to a printhead temperature signal line. The control unit 102 receives data from the temperature signal line and interprets the data to determine a single or multiple number of temperature measurements from the printhead 112. In some examples, the data provided by the temperature signal line is generated by a sensor (e.g., a thermistor) mounted on the printhead 112. Pin 30 is assigned as a printhead temperature return (PHTEMP RTN), which is a reference voltage to provide a return line for the temperature signal line assigned to pin 29. That is, pin 30 is coupled to a reference voltage.
By grouping the pins in the example groups shown in FIG. 8, the pin arrangement alternates 800 reference voltages (e.g., ground, PHTEMP RTN or VDD) with the signal lines. In particular, each of the groups or cable bundles contains at least one reference voltage and at least one single line. Alternating between the reference voltage among the different groups of pins in this way allows increased bandwidth (e.g. 350 MHz) for, for example, clock signal lines and data signal lines with reduced loss (e.g. -3 db). Furthermore, the grouping makes pins set in the exemplary pin arrangement of FIG. 8 efficient combing of the cable possible, which improves the mechanical throughput of the cable. The exemplary pin arrangement 800 of FIG. 8, for example, allows the cable to be combed
BE2017 / 5563 to be in accordance with the groupings set in FIG. 8 so that the cable is combed into six groups, one having eight lines, three having 6 lines and another having four lines (e.g., 8-6-6-6-4). Since each group or cable bundle contains at least one reference voltage, the effective loop area between the signal lines and the corresponding return (e.g., ground) is reduced. The reduced loop area lowers the induction and creates a more consistent impedance for the signal lines (e.g., high-speed signal lines). As such, with a lower induction, interference (e.g., interconnection) between signals is lowered.
FIG. 10 is a third exemplary pin arrangement 1000 for an exemplary communication arrangement depicted in FIG. 7 which includes that the control unit 102 (FIG. 1) is coupled to the adapter 500 (FIG. 5) via a 40-pin connector 700. The exemplary pin arrangement 1000 of FIG. 10 contains destinations for each of the forty (40) pins of the exemplary connections depicted in FIG. 7. The exemplary pin arrangement 1000 of FIG. 10 contains groups of pins depicted with a shared hatch in FIG. 10. In the example of FIG. 10 contains a first group of pins 1-3, a second group contains pins 4-7, a third group contains pins 8-12, a fourth group contains pins 13-16, a fifth group contains pins 17-20 and a sixth group contains pins 21-24, a seventh group contains 25-27, an eighth group contains 28-31, a ninth group contains 32-34, a tenth group contains 35-38 and an eleventh group contains 39 and 40.
The pin assignments (e.g., which pins are assigned to data signal lines, which pins are assigned to clock signal lines, which pins are assigned to reference voltages, etc.) in FIG. 10 are the same as the pentoe we sing from FIG. 6. As in the example pin arrangement 600 of FIG. 6, the pin arrangement alternates 1000 reference voltages (e.g., GND or VDD) with signal lines (e.g., latch signal lines, clock signal lines, strobe signal lines, etc.). In the
BE2017 / 5563 particularly, each group of the exemplary pin arrangement 1000 contains at least one reference voltage and at least one signal line, thereby lowering the induction paths required for higher speed signaling and EMI reduction.
FIG. 11 is a fourth exemplary pin arrangement 1100 for an exemplary communication arrangement depicted in FIG. 9 which includes that the control unit 102 (FIG. 1) is coupled to the print assembly 108 via the 30-pin connector 900. The exemplary pin arrangement 1100 of FIG. 11 contains destinations for each of the thirty (30) pins of the exemplary connections depicted in FIG. 9. The exemplary pin arrangement 1100 of FIG. 11 contains groups of pins shown with a shared shading in FIG. 11. In the example of FIG. 11 contains a first group of pins 1-4, a second group contains pins 5-8, a third group contains pins 9-11, a fourth group contains pins 12-14, a fifth group contains pins 15-17 and a sixth group contains pins 18-20, a seventh group contains 21-23, an eighth group contains 24-26, a ninth group contains 27-28 and a tenth group contains 29-30.
The assignment of the pins in FIG. 11 is the same as the pin assignment in FIG. 8. The exemplary pin arrangement 1100 of FIG. 11, however, contains different groups of pins than the exemplary pin arrangement 800 of FIG. 8. As in the example pin arrangement 800 of FIG. 8, the exemplary pin arrangement 1100 of FIG. 11 reference voltages with signal lines. In particular, each group of the exemplary pin arrangement 1100 includes at least one reference voltage and at least one signal line, thereby lowering the induction paths required for higher speed signaling and EMI reduction.
FIG. 12 is a block diagram representative of an exemplary logic circuit that can be used to control, for example, the control unit 102 of FIG. 1 and / or the control unit 110 of FIG. 1 to implement. The exemplary logic circuit of FIG. 12 is one
BE2017 / 5563 processing platform 1200 with the ability to execute instructions to, for example, print commands from the media processing apparatus 100 of FIG. 1 to implement.
The exemplary processing platform 1200 of FIG. 12 includes a processor 1202 such as, for example, one or more microprocessors, control units and / or any possible processor type. The exemplary processing platform 1200 of FIG. 12 contains memory (e.g., volatile memory, non-volatile memory) accessible to the processor 1202 (e.g., via a memory controller). The exemplary processor 1202 interacts with the memory 1204 to obtain, for example, machine-readable instructions stored in the memory 1204 according to, for example, print commands from the exemplary media processing apparatus 100 of FIG. 1. Additionally or alternatively, machine-readable instructions may be stored on a single or multiple number of removable media (e.g., a CD, a digitally versatile usable disc, removable flash memory, etc.) that may be coupled to the processing platform 1200 to access provide the machine-readable instructions stored thereon.
The exemplary processing platform 1200 of FIG. 12 includes a network interface 1206 to enable communication with other machines via, for example, one or more networks. The exemplary network interface 1206 includes any suitable type of communication interface (s) (e.g., wired and / or wireless interfaces) configured to operate in accordance with any suitable protocol.
The exemplary processing platform 1200 of FIG. 12 includes input / output (I / O) interfaces 1208 to enable receipt of user input and communication of output data to the user.
As used herein, each of the terms "tactile machine-readable medium", "non-volatile machine-readable medium" and "machine-readable storage device" is expressly described as a storage medium
BE2017 / 5563 (e.g., a hard disk drive plate, a digitally versatile disk, a CD, flash memory, read-only memory, random-access memory, etc.) on which machine-readable instructions (e.g., program code in the form of, for example, software and / or firmware). Furthermore, as used herein, each of the terms "tactile machine-readable medium", "non-volatile machine-readable medium" and "machine-readable storage device" is expressly described to exclude propagating signals. Which means, as used in each of the claims of this patent, that a "tangible machine-readable medium" cannot be read as implemented by a propagating signal. Furthermore, as used in any of the claims of this patent, a "non-volatile machine-readable medium" cannot be read as implemented by a propagating signal. Furthermore, as used in any of the claims of this patent, a "machine-readable storage device" cannot be read as implemented by a propagating signal.
As used herein, each of the terms "tactile machine-readable medium", "non-volatile machine-readable medium" and "machine-readable storage device" is expressly described as a storage medium on which machine-readable instructions are stored for any suitable amount of time (e.g., permanent, for an extended period of time (e.g., as long as a program in accordance with the machine-readable instruction is in progress) and / or a short period of time (e.g., as long as the machine-readable instructions are cached and / or during a buffering process)).
Although some exemplary devices, methods, and articles of manufacture are described herein, the scope of this patent is not limited thereto. On the contrary, this patent covers all devices, methods and articles of manufacture that reasonably fall within the scope of the claims of this patent. For the purpose of clarity and a
BE2017 / 5563 Brief description, features described herein are part of the same or different embodiments, however, it is noted that the scope of the invention may include embodiments with combinations of all or some of the features described. It can be understood that the embodiments shown have the same or similar parts, separately from where it is described that they are different. In the claims, a reference number in parentheses will not be considered as limiting the claim. The word contain or include does not exclude the presence of features or steps other than those present in the claim. Furthermore, the word "one" should not be understood as "only one", but used to mean at least one, and does not exclude a plural. The fact that certain sizes are mentioned in mutually different claims does not indicate that a combination of these sizes cannot be used to an advantage. A multitude of variants are apparent to those skilled in the art. All variants are understood to fall within the scope of the invention which is defined in the following claims.

权利要求:
Claims (22)
[1]
CONCLUSIONS
A printhead assembly comprising:
- an interface for placing the printhead assembly in communication with a logic circuit of a printer; and
- a logic circuit configured according to a pin arrangement, wherein the pin arrangement comprises pin groups, the pin groups being defined on the basis of which pins of the pin arrangement are to be bundled together in a cable bundle, and wherein each of the pin groups contains a signal line and a reference voltage .
[2]
The printhead assembly according to claim 1, wherein the pin arrangement comprises forty pins and eleven pin groups.
[3]
The printhead assembly according to claim 1 or 2, wherein the pin arrangement comprises ten data pins.
[4]
The printhead assembly according to any of the preceding claims, wherein the pin arrangement comprises five clock pins.
[5]
The printhead assembly according to any of the preceding claims, wherein the pin arrangement comprises first and second latch pins.
[6]
The printhead assembly of claim 5, wherein the first latch pin is assigned to a first pin group and the second latch pin is assigned to a second pin group.
[7]
A printhead assembly according to any one of the preceding claims, wherein the pin arrangement comprises first and second strobe pins.
[8]
The printhead assembly of claim 7, wherein the first strobe pin is assigned to a first pin group and the second strobe pin is assigned to a second pin group.
[9]
The printhead assembly of claim 1, wherein the pin arrangement comprises thirty pins and ten pin groups.
[10]
The printhead assembly of any one of the preceding claims, wherein
BE2017 / 5563 the reference voltage is a first reference voltage and each of a plurality of pin groups contains the first reference voltage and a second reference voltage that differs from the first reference voltage.
[11]
11. Printhead assembly according to one of the preceding claims, wherein the logic circuit implements a control unit for a printhead with heating elements.
[12]
A media processing device comprising:
- memory including machine-readable instructions; and
- a processor to execute machine-readable instructions to control a printhead assembly, the processor configured to communicate with the printhead assembly in accordance with a pen arrangement, the pen arrangement comprising pin groups, the pin groups being defined based on which pins of the pin arrangement must be bundled together in a cable bundle and each of the pin groups contains a signal line and a reference voltage.
[13]
The media processing apparatus of claim 12, wherein the pin arrangement includes forty pins and eleven pin groups.
[14]
The media processing apparatus according to claims 12 or 13, wherein the pin arrangement comprises ten data pins.
[15]
The media processing apparatus according to any of claims 12-14, wherein the pin arrangement comprises five clock pins.
[16]
The media processing apparatus of any one of claims 12-15, wherein the pin arrangement includes first and second latch pins.
[17]
The media processing apparatus of claim 16, wherein the first latch pin is assigned to a first pin group and the second latch pin is assigned to a second pin group.
[18]
The media processing apparatus of any one of claims 12-17, wherein the pin arrangement includes first and second strobe pins.
[19]
The media processing apparatus of claim 18, wherein the first strobe pin is assigned to a first pin group and the second strobe pin to
BE2017 / 5563 a second pin group has been assigned.
[20]
The media processing apparatus of claim 12, wherein the pin arrangement comprises thirty pins and ten pin groups.
[21]
A media processing device according to any of claims 12-20,
5 wherein the reference voltage is a first reference voltage and each of a plurality of pin groups contains the first reference voltage and a second reference voltage that differs from the first reference voltage.
[22]
The printhead assembly of claim 1, wherein the pin arrangement includes a plurality of clock pins.

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同族专利:

公开号 | 公开日

US20200147963A1|2020-05-14|

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US20180050538A1|2018-02-22|

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CN109562625B|2020-11-27|

BE1025218A1|2018-12-05|

CN109562625A|2019-04-02|

US10569542B2|2020-02-25|

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法律状态:
2019-01-16| FG| Patent granted|Effective date: 20181212 |

2019-05-02| PD| Change of ownership|Owner name: ZEBRA TECHNOLOGIES CORPORATION; US Free format text: DETAILS ASSIGNMENT: CHANGE OF OWNER(S), FUSION; FORMER OWNER NAME: ZIH CORP. Effective date: 20190225 |

优先权:

申请号 | 申请日 | 专利标题

US15/238,290|US10569542B2|2016-08-16|2016-08-16|Printhead pin configurations|

US15238290|2016-08-16|

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